Power Control register
| PM0 | Power mode control bit 0. This bit controls entry to the Power-down mode. See Section 3.3.6.1 below for details. |
| PM1 | Power mode control bit 1. This bit controls entry to the Deep Power-down mode. See Section 3.3.6.1 below for details. |
| BODRPM | Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection. |
| BOGD | Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| BORD | Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. See the Section 3.6 for details of Brown-Out detection. |
| SMFLAG | Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit. |
| DSFLAG | Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit. |
| PDFLAG | Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit. |
| DPDFLAG | Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |